Computer organisation & architecture (processor, registers, assembly language) – A-level Computer Science exam questions with mark scheme

1Core4 marks

Describe the fetch stage of the fetch-execute cycle in a processor with a Von Neumann architecture. [4]

The address held in the program counter (PC) is copied to the memory address register (MAR) (allow: address sent along the address bus)(1)
The PC is incremented (to point at the next instruction) (allow at any point after the PC has been copied to the MAR)(1)
The instruction at that address is read from main memory (allow: read signal on the control bus) and copied via the data bus into the memory buffer register (MBR) (accept memory data register / MDR)(1)
The contents of the MBR are copied to the current instruction register (CIR) (accept MDR for MBR)(1)
Answer: PC to MAR; PC incremented; instruction from memory to MBR; MBR to CIR
Examiner tip: Name each register and say what moves into it; "the instruction is fetched" alone earns nothing.

2Core5 marks

(a) Name the bus that: [3]

(b) A processor has a 20-bit address bus. Calculate the number of memory locations it can address. [2]

(i) Address bus(1)
(ii) Data bus(1)
(iii) Control bus(1)
2²⁰ (one location per distinct address) (correct final answer with no working scores 2 marks)(1)
1 048 576 (accept 1 Mi / 1 mebi locations; reject 1 048 575, which is the highest address, 1 000 000, and 20 × 2 = 40)(1)
Answer: (a) address, data, control (b) 1 048 576
Examiner tip: Number of locations is 2 to the power of the bus width, not 20 × 2.

3Standard4 marks

The table shows the contents of memory locations before a program runs. A program is run using the AQA assembly language instruction set.

Address	100	101	102
Contents	14	9	0

LDR R0, 100
LDR R1, 101
ADD R2, R0, R1
SUB R2, R2, #5
STR R2, 102
HALT

(a) State the value in R2 after the ADD instruction executes. [1]

(b) State the value in R2 after the SUB instruction and the value stored in location 102 when the program ends. [2]

23(1)
18 in R2 after SUB(1)
18 in location 102 (after STR)(1)
Stops the program / processor execution(1)
Answer: (a) 23 (b) R2 = 18, location 102 = 18 (c) stops execution
Examiner tip: Remember that SUB R2, R2, #5 overwrites R2; students often keep 23 for the store.

4Standard5 marks

      MOV R0, #1
      MOV R1, #0
loop: ADD R1, R1, R0
      ADD R0, R0, #1
      CMP R0, #5
      BLT loop
      HALT

(a) State the final values in R0 and R1 when the program halts. [2]

(b) State how many times the instruction ADD R1, R1, R0 is executed. [1]

(d) State the change needed so that the program calculates the sum of the integers from 1 to 10. [1]

R0 = 5(1)
R1 = 10(1)
4 times(1)
Calculates the sum of the integers 1 to 4 (accept 1+2+3+4)(1)
Change CMP R0, #5 to CMP R0, #11 (accept 'change the 5 in the CMP instruction to 11'; reject CMP R0, #10, which gives 1 to 9)(1)
Answer: (a) R0 = 5, R1 = 10 (b) 4 (c) sum of 1 to 4 (d) CMP R0, #11
Examiner tip: BLT loops while R0 is less than 5, so the last value added is 4, not 5.

5Hard5 marks

Memory location 200 contains the binary value 10110111.

LDR R0, 200
AND R1, R0, #15
LSL R2, R1, #2
EOR R3, R2, #255
HALT

(a) Give the denary values in R1, R2 and R3 after the program halts. [3]

(b) State the effect of the instruction LSL R2, R1, #2 in terms of multiplication. [1]

R1 = 7 (00000111)(1)
R2 = 28 (00011100)(1)
R3 = 227 (11100011)(1)
Multiplies by 2² (= 4) (accept: shifts the bits 2 places left so the value is ×4)(1)
Inverts every bit (accept: bitwise NOT / same as MVN / flips each 0 to 1 and each 1 to 0)(1)
Answer: (a) 7, 28, 227 (b) ×4 (c) inverts all 8 bits
Examiner tip: Write the bit patterns out beneath each other; AND with 15 keeps only the lower four bits.

6Stretch6 marks

Write an assembly language program, using the AQA instruction set, that:

[6]

LDR R0, 300 (loads the number)(1)
CMP R0, #50(1)
BGT to a label for the greater-than case (branch condition correct for the layout used)(1)
MOV R1, #0 in the not-greater case, followed by an unconditional B past the other case (allow any equivalent structure, e.g. MOV R1, #0 first and then overwrite with MOV R1, #1 on the greater path)(1)
MOV R1, #1 at the greater-than label(1)
STR R1, 301 reached by both paths, then HALT(1)
Answer: e.g. LDR R0,300 / CMP R0,#50 / BGT big / MOV R1,#0 / B end / big: MOV R1,#1 / end: STR R1,301 / HALT
Examiner tip: Without the unconditional B end, the not-greater path falls through and overwrites R1 with 1.

7Standard4 marks

A computer's performance is improved by adding more processor cores and a larger cache.

Explain how each change can improve performance. [4]

More cores allow more instructions to be executed at the same time (parallel processing)(1)
So different tasks or threads are processed simultaneously, so more instructions are completed per second / the total time taken is reduced (ignore a bare statement that software must be written to use multiple cores unless linked to this benefit)(1)
Cache is (small) memory that is faster to access than main memory, located on / close to the processor(1)
Larger cache holds more frequently used instructions/data, so fewer slower accesses to main memory (RAM) are needed (accept: higher hit rate)(1)
Answer: More cores: parallel execution; larger cache: more data quickly available, fewer main memory accesses
Examiner tip: Link each change to its mechanism; "faster" alone is not enough.

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